Low power enhancements for parallel algorithms
نویسندگان
چکیده
In this paper we present a general approach for reducing switching activity on the algorithmic level. We concentrate on iterative algorithms that are suitable for an implementation on parallel processor arrays. The reduction is substantially reached by avoiding operations that hardly contribute to the convergence of the implemented algorithm. Our general approach is exemplified on the implementation of a specific algorithm, i.e. the eigenvalue decomposition (EVD) of a real symmetric matrix.
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تاریخ انتشار 2001